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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-28. Switching Characteristics for I2C Timings (1) (see Figure 5-28 )
CV DD = 1.05 V
CV DD = 1.3 V
NO.
PARAMETER
STANDARD
MODE
MIN
MAX
FAST MODE
MIN
MAX
UNIT
16
17
18
19
20
21
t c(SCL)
t d(SCLH-SDAL)
t d(SDAL-SCLL)
t w(SCLL)
t w(SCLH)
t d(SDAV-SCLH)
Cycle time, SCL
Delay time, SCL high to SDA low (for a repeated START
condition)
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
10
4.7
4
4.7
4
250
2.5
0.6
0.6
1.3
0.6
100
μs
μs
μs
μs
μs
ns
22
t v(SCLL-SDAV)
Valid time, SDA valid after SCL low
0
0
0.9
μs
23
24
t w(SDAH)
t r(SDA)
Pulse duration, SDA high between STOP and START
conditions
Rise time, SDA (2)
4.7
1000 20 + 0.1C b (1)
1.3
300
μs
ns
25
t r(SCL)
Rise time, SCL
(2)
1000 20 + 0.1C b
(1)
300
ns
26
27
28
29
t f(SDA)
t f(SCL)
t d(SCLH-SDAH)
C p
Fall time, SDA (2)
Fall time, SCL (2)
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
300 20 + 0.1C b (1)
300 20 + 0.1C b (1)
10
0.6
300
300
10
ns
ns
μs
pF
(1)
(2)
C b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
The rise/fall times are measured at 30% and 70% of DV DDIO . The fall time is only slightly influenced by the external bus load (C b ) and
external pullup resistor. However, the rise time (t r ) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
SDA
26
23
21
24
25
19
20
28
SCL
16
18
22
27
18
17
Stop
Start
Repeated
Stop
Start
Figure 5-28. I2C Transmit Timings
Copyright ? 2010–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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